1. Introduction

The processing of Silicon wafers to produce XMR (AMR / GMR / TMR) sensors involves a good deal of chemistry and physics.  In order to alter the surface conditions and properties, it is necessary to use both inert and toxic chemicals, specific and unusual conditions, and to manipulate those conditions with both plasma-state elements and with RF (Radio Frequency) energies. Starting with thin, round wafers of silicon crystal, in diameters of 150, 200 mm, the processes described here build up a succession of layers of materials and geometries to produce thousands of electronic devices at tiny sizes, which together function as sensors. The devices which now occupy the surface of a one-inch square IC would have occupied the better part of a medium-sized room 20 years ago, when all these devices (transistors, resistors, capacitors, and so on) were only available as discreet units.

The conditions under which these processes can work to successfully transform the silicon into ICs require an absolute absence of contaminants. Thus, the process chambers normally operate under vacuum, with elemental, molecular, and other particulate contaminants rigorously controlled. In order to understand these processes, then, we will begin the study of semiconductor processing with an overview of vacuum systems and theory, of gas systems and theory, as applied specifically to these tools, and of clean room processes and procedures.

2. Wafer FAB Design

Both capital and operation costs of wafer fabs are increasing significantly. In 1980, building a new wafer fab required an investment of 100 million US-dollars. In 1998, roughly speaking, one new eight-inch wafer fab took an investment of over 1000 million US-dollars. This tremendous increase in cost can be explained by the ongoing advances that are being made in developing new technologies.  As a consequence, machines that produce wafers are becoming more and more expensive. 

The main drive to overcome increased wafer costs is the reduction of the feature size of the transistors and wires in the IC. Smaller feature sizes enable more ICs to be made on one wafer. Furthermore, there is a drive for integrating IC functionality.

In spite of the huge investments required to build a wafer fab, the manufacturing costs for a single chip can range from only one to up to twenty dollars, which is considered to be low.

Initiation of a wafer fab starts with a top-level management decision that capacity is required and that in-house production is the way to achieve this.  The business plan identifies which types of products are to be made and in what quantities. The business plan also contains evaluation of alternatives and a reliability study. Before the project is started, it must be known if it is economically interesting. Outcomes of the business plan are the required resources (machines and people), target cycle times, and production specifications. The budget allocation for construction of the facility must then be determined in order to establish the boundary conditions that determine the profitability of the new fab. Once the business issues are resolved, a list of requirements can be reviewed. The facility requirements can be translated into various architectural and engineering solutions by designers.

From a project management point of view, the following phases can be identified in the constitution of a wafer fab: ground breaking, which ends with a weather proof building; clean room building; machine move in and qualification; start of the first silicon and first silicon out of the fab; full process qualification; and production ramp to full capacity. 

Advancing through these stages, the design of the wafer fab must become more specific. As can be seen from the description of these phases of a fab, the level of abstraction is lower as time advances. Before ground breaking can start, a structure of the fab needs to be available.  Before machine installation starts, the layout of the fab needs to be clear.

That is to say, a first version of that layout. As not all machines are placed at the same time in the fab, layout can and will change due to altered circumstances in the fab or in the fab's environment. When nearly all machines have been placed in the fab, optimization cycles are required for continuous improvement.

There is a trend towards automation of the wafer fabrication process. Ergonomic reasons form one of the major arguments for this trend. In mechanical sense this means that the wafer transport is automated. In logistical sense this means that the wafer flow control, that is, planning and scheduling, and equipment control are auto- mated.

Consequences of mechanization and automation are that a degree of freedom is taken away.  Once specified and built, these systems provide few opportunities to adapt easily to changing requirements.  The importance of fab design - illustrated by the diminishing flexibility - is opposed to the required flexibility as demanded by the market.

The above shows requirements for the design process.  It illustrates the need for a design method and for design tools that support the design process during all phases. The design implications of many critical decisions made early in the design stages of a new semiconductor wafer fab can and do have a significant impact on both the initial and operating costs. The ability to influence the project costs decreases dramatically as the project gets underway.

Engineering consultants have prepared useful draft designs for fab layouts, based on process and machine characteristics and on their experience.  Refining these drafts, however, is always necessary, because process technologies will develop and new insights on how to run the fab will develop. Only the semiconductor manufacturer has the required in-depth knowledge, and therefore must be the generator of the organization and consequently the logistics of the fab.

Literature shows little references on the design of IC wafer fabs. Methods for layout determination are known since the 1960s, Apple [1963], Burbidge [1971], and Muther [1973] present general design methods.  However, they are straightforward and are focussed on the goods flow.  The control system is not considered in these design approaches. Recently, more sophisticated optimization methods for layout design have been explored.

These methods still focus on the layout and the primary goods fiow only.  They take the conceptual architecture of the wafer fab as the starting point for their optimization, while it is this starting point that should be questioned.

The control of wafer fabs can be divided into planning and scheduling. The planning level concerns the interaction with the environment, the translation of customer orders to fab dobs, and capacity planning. The scheduling is primarily focussed on controlling the shop floor. The literature review on semiconductor planning by Uzsoy, Lee & Martin-Vega [1992] shows that it is the planning level that gets almost no attention in literature.  The control of wafer fabs is extensively discussed in the terms of scheduling.

Today, most integrated circuits (ICs) are made of silicon. Turning silicon into memory chips is an exacting, meticulous procedure involving engineers, metallurgists, chemists and physicists. The first step from silicon to circuit is the creation of a pure, single-crystal cylinder or ingot of silicon six to eight inches in diameter. These cylinders are sliced into thin, highly polished wafers less than one-fortieth of an inch thick. Micron uses six- and eight-inch wafers. The circuit elements (transistors, resistors, and capacitors) are built in layers on the silicon wafer. Hundreds of memory chips are etched onto each wafer. Pure single-crystal cylinders of silicon are sliced into thin, highly polished wafers less than one-fortieth of an inch thick. Hundreds of memory chips are etched onto each wafer, while for processor chips, perhaps only ten to 50 devices will fit on one wafer. Most chip designs are developed with the help of computer systems or computer-aided design (CAD) systems. Circuits are developed, tested by simulation, and perfected on computer systems before they are actually built. When the design is complete, glass photo masks are made—one mask for each layer of the circuit. These glass photo masks are used in a process called photolithography.

3. Process Step

The complexity of wafer fabrication comes from the high-tech processes that are applied, the multitude of process steps and their recurrence, and the comprehensive control required. Common process technologies consist of 20 to 30 layers. Often, different layers are fabricated using the same set of machines.

-Wet Etching

Wet etching is done with the use of chemicals. A batch of wafers is dipped into a higly concentrated pool of acid and the exposed areas of the wafer are etched away. Wet etching is good in that it is fairly cheap and capable of processing many wafers quickly. The disadvantage is that wet etching does not allow the smaller critical geometries that are needed for today’s chips.

-CVD (PE-CVD)

In this sterile environment, the wafers are exposed to a multiple-step photolithography process that is repeated once for each mask required by the circuit. Each mask defines different parts of a transistor, capacitor, resistor, or connector composing the complete integrated circuit and defines the circuitry pattern for each layer on which the device is fabricated.

At the beginning of the production process, the bare silicon wafer is covered with a thin glass layer followed by a nitride layer. The glass layer is formed by exposing the silicon wafer to oxygen at temperatures of 900 degrees C or higher for an hour or more, depending on how thick a layer is required. Glass (silicon dioxide) is formed in the silicon material by exposing it to oxygen. At high temperatures, this chemical reaction (called oxidation) occurs at a much faster rate.

-Photolithography

Next, the wafer is uniformly coated with a thick light-sensitive liquid called photoresist. The coating is applied while the wafer is spinning. Portions of the wafer are selected for exposure by carefully aligning a mask between an ultraviolet light source and the wafer. In the transparent areas of the mask, light passes through and exposes the photoresist.

-Etching the Wafer Surface

The etching process is used immediately after photolithography to etch the unwanted material from the wafer.

This process is not selective and that is why the pattern had to be traced onto the wafer using photoresist.

There are two main methods of etching, wet etching and dry etching.  This leaves a pattern on the wafer in the exact design of the mask. The hardened photoresist is then removed (cleaned) with another chemical.

-Dry Etching

Dry etching refers to any of the methods of etching that use gas instead of chemical etchants. Dry etching is capable of producing critical geometries that are very small.

-Plasma Etching

Plasma etching uses a gas that is subjected to an intense electric field to generate the plasma state of matter. The electric field is produced with coils that are wrapped around the chamber and exposed to a high level RF source.

There are two different versions of this type of etching based on the shape of the chamber used. One consists of a barrel type chamber where the wafers are placed sitting up while the gas is flowed over the wafers and out through an exhaust pipe. The second process uses a parallel plate reactor. There are two plates that are used to give the gas the electric field rather than the coil that is wrapped around the barrel chamber. In plasma form, the gases used are very reactive, providing effective etching of the exposed surface.  Plasma etching provides good critical geometry but the wafer can be damaged from the RF radiation.

-Reactive Ion Etching

This method works at a lower pressure and uses a combined physical and chemical method to etch the wafer.

-Ion Milling

Ion milling uses electric and magnetic fields to cause the plasma ions to form a beam that is used to do the etching. This method is extremely accurate and has the ability to reach very small critical geometries.

-Implant / Masking Steps:  Diffusion & Ion Implant

Electrical characteristics of selected areas on the developing integrated circuit are changed by implanting energized ions (dopants) in the form of specific impurities into areas not protected by resist or other layers. The dopants come to rest below the wafer's surface, creating the positive and negative areas on the wafer which encourage or discourage the flow of electrical current throughout the die. These basic steps are repeated for additional layers of poly silicon, glass, and aluminum.

These processes can be damaging to the wafer, so a heating process known as annealing is used to reduce any damage to the wafers.

-Diffusion

Diffusion is done in a furnace with a flow of gas running over the wafers. This step, like etch, is not selective so the photoresist and patterning need to be done before this step. The best way to understand the processes of this step is to imagine oxidation. Diffusion is very similar to oxidation except using a different gas other than oxygen.

-Ion Implantation

Ion implantation is different from diffusion. Diffusion uses the natural state of gas going to where there is no gas, while ion implantation shoots the desired dopant ions into the wafer. Ion implantation has been best equated with firing a machine gun into a wall. In this analogy the wall is the wafer and the bullets are the ions. The main disadvantage of ion implantation is that it can only process a single wafer at a time while a diffusion chamber is capable of handling many wafers.

-Annealing

Due to the incredible damage that these processes (especially ion implantation) can cause to the wafer an addition alstage of heating is required. During this final stage the wafer is heated so that the crystal lattice structure of the wafer will repair itself. The finished wafer is an intricate sandwich of n-type and p-type silicon and insulating layers of glass and silicon nitride. All of the circuit elements (transistor, resistor, and capacitor) are constructed during the first few mask operations. The next masking steps connect these circuit elements together. An insulating layer of glass (called BPSG) is deposited and a contact mask is used to define the contact points or windows of each of the circuit elements. After the contact windows are etched, the entire wafer is covered with a thin layer of aluminum in a sputtering chamber. The metal mask is used to define the aluminum layer leaving a fine network of thin metal connections or wires. The entire wafer is then covered with an insulating layer of glass and silicon nitride to protect it from contamination during assembly. This protective coating is called the passivation layer. The final mask and passivation etch removes the passivation material from the terminals, called bonding pads.

The bonding pads are used to electrically connect the die to the metal pins of the plastic or ceramic package.

While still on the wafer, every integrated circuit is tested and functional and nonfunctional chips are identified and mapped into a computer data file. A diamond saw then cuts the wafer into individual chips. Nonfunctional chips are discarded and the rest are sent on to be assembled into plastic packages.

-Final Testing / Shipping

Each memory chip is tested at various stages in the manufacturing process to see how fast it can store or retrieve information, including the high temperature burn-in in MDT's proprietary AMBYX® ovens which test the circuitry of each chip, ensuring the quality and reliability. This monitored burn-in provides feedback throughout the process, allowing identification and correction of manufacturing problems. The completed packages are inspected, sealed, and marked with a special ink to indicate product type, date, package code, and speed. The finished goods area ships the chips to computer, peripheral, telecommunications, and transportation customers throughout the world. In the last 30 years semiconductors have become virtually indispensable in many aspects of daily life. Even people who do not own or use a computer are likely to use semiconductor memory in one way or another.

Many of the fantastic capabilities of our modern world are possible thanks to the semiconductor memory chip.

Reference : Dr. Seth P. Bates, Silicon Wafer Process, Applied Materials, Summer, 2000